The present invention relates to the field of semiconductor processing and more particularly to an improved process for automatically calibrating a masking process simulator.
An integrated circuit is fabricated by translating a circuit design or layout to a semiconductor substrate. In optical lithography, the layout is first transferred onto a physical template, which is in turn used to optically project the layout onto a silicon wafer. In transferring the layout to a physical template, a mask is generally created for each layer of the integrated circuit design. The patterned photomask includes transparent, attenuated phase shifted, phase shifted, and opaque areas for selectively exposing regions of the photoresist-coated wafer to an energy source. To fabricate a particular layer of the design, the corresponding mask is placed over the wafer and a stepper or scanner machine shines a light through the mask from the energy source. The end result is a semiconductor wafer coated with a photoresist layer having the desired pattern that defines the geometries, features, lines and shapes of that layer. The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate. This process is then repeated for each layer of the design.
Ideally, the photoresist pattern produced by the photolithography process and the substrate pattern produced by the subsequent etch process would precisely duplicate the pattern on the photomask. For a variety of reasons, however, the photoresist pattern remaining after the resist develop step may vary from the pattern of the photomask significantly. Diffraction effects and variations in the photolithography process parameters typically result in critical dimension (CD) variation from line to line depending upon the line pitch of the surrounding environment (where pitch is defined for purposes of this disclosure as the displacement between an adjacent pair of interconnect lines). In addition to CD variation, fringing effects and other process variations can result in end-of-line effects (in which the terminal end of an interconnect line in the pattern is shortened or cut off by the photolithography process) and corner rounding (in which square angles in the photomask translate into rounded corners in the pattern). These three primary optical proximity effects, together with other photoresist phenomena such as notching, combine to undesirably produce a patterned photoresist layer that may vary significantly from the pattern of the photomask. In addition to variations introduced during the photolithography process, further variations and distortions are typically introduced during the subsequent etch process such that the pattern produced in the semiconductor substrate may vary from the photomask pattern even more than the photoresist pattern.
Conventional semiconductor process engineering in the areas of photolithography and etch typically attempts to obtain a finished pattern that approximates the desired pattern as closely as possible by controllably altering the process parameters associated with the various masking steps. Among the parameters process engineers typically attempt to vary in an effort to produce a photoresist pattern substantially identical to the photomask pattern include the intensity, coherency and wave length of the energy source, the type of photoresist, the temperature at which the photoresist is heated prior to exposure (pre-bake), the dose (intensityxc3x97time) of the exposing energy, the numerical aperture of the lens used in the optical aligner, the use of antireflective coatings, the develop time, developer concentration, developer temperature, developer agitation method, post bake temperature, and a variety of other parameters associated with the photolithography process. Etch parameters subject to variation may include, for example, process pressure and temperature, concentration and composition of the etch species, and the application of a radio frequency energy field within the etch chamber.
Despite their best efforts, however, semiconductor process engineers are typically unable to manipulate the photolithography and etch processes such that the photoresist and substrate patterns produced by the processes are substantially identical to the photomask pattern.
To avoid the time and cost of producing actual test wafers for every desired permutation of process parameters, computerized simulation of masking processes is employed to facilitate the optimization of a particular masking sequence and the generation of an optical proximity correction (OPC) distorted photomask. Masking process simulators receive various inputs corresponding to the parameters of the photoresist and etch processes to be simulated and attempt to simulate the pattern that will be produced by the specified masking process given a particular photomask. Accordingly, computerization has significantly enhanced the process engineer""s ability to characterize and optimize masking processes.
Nevertheless, it is typically impossible to adequately account for the multitude of parameters associated with a masking process despite the effort devoted to masking process characterization, the introduction of optical proximity correction techniques, and the emergence of sophisticated process simulation software. In other words, simulation programs are ultimately unable to account for the various parametric dependencies in a manner sufficient to predict the exact pattern that will be produced by any particular masking process and mask.
Accordingly, what is needed is a method and system for improving the prediction accuracy of masking process simulator software. The present invention addresses such a need.
The present invention provides a method and system for improving the prediction accuracy of masking process simulators through automatic calibration of the simulators. The method and system include performing a masking process using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected from the digital image using pattern recognition. Data defining the calibration mask and the process parameters are then input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The method and system further include overlaying the alim image and the detected edges of the digital image, and measuring a distance between contours of the pattern in the alim image and the detected edges. Thereafter, one or more mathematical algorithms are used to iteratively change the values of the processing parameters input to the simulator until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.
According to the method and system disclosed herein, the calibration effectively calibrates the process simulator to compensate for process variations of the masking process. Once the calibration is performed and actual mask data and the modified process parameters are input to the process simulator, the process simulator will produce an image that varies minimally from the actual pattern produced by the masking process.